// ****************************************************************************** 
// Copyright     :  Copyright (C) 2018, Hisilicon Technologies Co. Ltd.
// File name     :  vpc_top_nmanager_reg_offset_field.h
// Project line  :  Platform And Key Technologies Development
// Department    :  CAD Development Department
// Author        :  xxx
// Version       :  1.0
// Date          :  2013/3/10
// Description   :  The description of xxx project
// Others        :  Generated automatically by nManager V4.2 
// History       :  xxx 2018/03/19 14:40:32 Create file
// ******************************************************************************

#ifndef __VPC_TOP_NMANAGER_REG_OFFSET_FIELD_H__
#define __VPC_TOP_NMANAGER_REG_OFFSET_FIELD_H__

#define VPC_TOP_NMANAGER_VPC_RDMA_START_LEN    1
#define VPC_TOP_NMANAGER_VPC_RDMA_START_OFFSET 0

#define VPC_TOP_NMANAGER_RDMA_CVDR_RD_SEL_LEN    1
#define VPC_TOP_NMANAGER_RDMA_CVDR_RD_SEL_OFFSET 16
#define VPC_TOP_NMANAGER_VCPI_AXI_OD_CFG_LEN     5
#define VPC_TOP_NMANAGER_VCPI_AXI_OD_CFG_OFFSET  11
#define VPC_TOP_NMANAGER_VCPI_AXI_STOP_OK_LEN    1
#define VPC_TOP_NMANAGER_VCPI_AXI_STOP_OK_OFFSET 10
#define VPC_TOP_NMANAGER_VCPI_AXI_STOP_EN_LEN    1
#define VPC_TOP_NMANAGER_VCPI_AXI_STOP_EN_OFFSET 9
#define VPC_TOP_NMANAGER_IN_BITWIDTH_CFG_LEN     1
#define VPC_TOP_NMANAGER_IN_BITWIDTH_CFG_OFFSET  8
#define VPC_TOP_NMANAGER_IN_FORMAT_CFG_LEN       3
#define VPC_TOP_NMANAGER_IN_FORMAT_CFG_OFFSET    0

#define VPC_TOP_NMANAGER_VPC_FORCE_CLK_ON_LEN          1
#define VPC_TOP_NMANAGER_VPC_FORCE_CLK_ON_OFFSET       16
#define VPC_TOP_NMANAGER_VCPI_HFBCD_CLK_GT_EN_LEN      1
#define VPC_TOP_NMANAGER_VCPI_HFBCD_CLK_GT_EN_OFFSET   1
#define VPC_TOP_NMANAGER_RDMA_LINEBUF_CLK_GT_EN_LEN    1
#define VPC_TOP_NMANAGER_RDMA_LINEBUF_CLK_GT_EN_OFFSET 0

#define VPC_TOP_NMANAGER_VCPI_SRCYH_ADDR_LEN    32
#define VPC_TOP_NMANAGER_VCPI_SRCYH_ADDR_OFFSET 0

#define VPC_TOP_NMANAGER_VCPI_SRCCH_ADDR_LEN    32
#define VPC_TOP_NMANAGER_VCPI_SRCCH_ADDR_OFFSET 0

#define VPC_TOP_NMANAGER_VCPI_SRCCH_STRIDE_LEN    16
#define VPC_TOP_NMANAGER_VCPI_SRCCH_STRIDE_OFFSET 16
#define VPC_TOP_NMANAGER_VCPI_SRCYH_STRIDE_LEN    16
#define VPC_TOP_NMANAGER_VCPI_SRCYH_STRIDE_OFFSET 0

#define VPC_TOP_NMANAGER_VCPI_SRCY_ADDR_LEN    32
#define VPC_TOP_NMANAGER_VCPI_SRCY_ADDR_OFFSET 0

#define VPC_TOP_NMANAGER_VCPI_SRCC_ADDR_LEN    32
#define VPC_TOP_NMANAGER_VCPI_SRCC_ADDR_OFFSET 0

#define VPC_TOP_NMANAGER_VCPI_SRCC_STRIDE_LEN    16
#define VPC_TOP_NMANAGER_VCPI_SRCC_STRIDE_OFFSET 16
#define VPC_TOP_NMANAGER_VCPI_SRCY_STRIDE_LEN    16
#define VPC_TOP_NMANAGER_VCPI_SRCY_STRIDE_OFFSET 0

#define VPC_TOP_NMANAGER_VCPI_IMGHEIGHT_PIX_LEN    13
#define VPC_TOP_NMANAGER_VCPI_IMGHEIGHT_PIX_OFFSET 16
#define VPC_TOP_NMANAGER_VCPI_IMGWIDTH_PIX_LEN     13
#define VPC_TOP_NMANAGER_VCPI_IMGWIDTH_PIX_OFFSET  0

#define VPC_TOP_NMANAGER_VPC_CVDR_VP_WR_EOL_STA_LEN    5
#define VPC_TOP_NMANAGER_VPC_CVDR_VP_WR_EOL_STA_OFFSET 19
#define VPC_TOP_NMANAGER_VPC_CVDR_VP_WR_EOF_STA_LEN    5
#define VPC_TOP_NMANAGER_VPC_CVDR_VP_WR_EOF_STA_OFFSET 14
#define VPC_TOP_NMANAGER_VPC_CVDR_VP_WR_SOF_STA_LEN    5
#define VPC_TOP_NMANAGER_VPC_CVDR_VP_WR_SOF_STA_OFFSET 9
#define VPC_TOP_NMANAGER_VPC_CVDR_VP_RD_EOL_STA_LEN    3
#define VPC_TOP_NMANAGER_VPC_CVDR_VP_RD_EOL_STA_OFFSET 6
#define VPC_TOP_NMANAGER_VPC_CVDR_VP_RD_EOF_STA_LEN    3
#define VPC_TOP_NMANAGER_VPC_CVDR_VP_RD_EOF_STA_OFFSET 3
#define VPC_TOP_NMANAGER_VPC_CVDR_VP_RD_SOF_STA_LEN    3
#define VPC_TOP_NMANAGER_VPC_CVDR_VP_RD_SOF_STA_OFFSET 0

#define VPC_TOP_NMANAGER_VPC_EOF_INT1_STA_LEN              1
#define VPC_TOP_NMANAGER_VPC_EOF_INT1_STA_OFFSET           12
#define VPC_TOP_NMANAGER_VPC_EOF_INT2_STA_LEN              1
#define VPC_TOP_NMANAGER_VPC_EOF_INT2_STA_OFFSET           11
#define VPC_TOP_NMANAGER_VPC_RDMA_FRAME_END_STA_LEN        1
#define VPC_TOP_NMANAGER_VPC_RDMA_FRAME_END_STA_OFFSET     10
#define VPC_TOP_NMANAGER_VPC_PIPE_POSTCROP2_EOP_STA_LEN    1
#define VPC_TOP_NMANAGER_VPC_PIPE_POSTCROP2_EOP_STA_OFFSET 9
#define VPC_TOP_NMANAGER_VPC_PIPE_YUVSCALE2_EOF_STA_LEN    1
#define VPC_TOP_NMANAGER_VPC_PIPE_YUVSCALE2_EOF_STA_OFFSET 8
#define VPC_TOP_NMANAGER_VPC_PIPE_YUVSCALE2_SOF_STA_LEN    1
#define VPC_TOP_NMANAGER_VPC_PIPE_YUVSCALE2_SOF_STA_OFFSET 7
#define VPC_TOP_NMANAGER_VPC_PIPE_POSTCROP1_EOP_STA_LEN    1
#define VPC_TOP_NMANAGER_VPC_PIPE_POSTCROP1_EOP_STA_OFFSET 6
#define VPC_TOP_NMANAGER_VPC_PIPE_YUVSCALE_EOF_STA_LEN     1
#define VPC_TOP_NMANAGER_VPC_PIPE_YUVSCALE_EOF_STA_OFFSET  5
#define VPC_TOP_NMANAGER_VPC_PIPE_YUVSCALE_SOF_STA_LEN     1
#define VPC_TOP_NMANAGER_VPC_PIPE_YUVSCALE_SOF_STA_OFFSET  4
#define VPC_TOP_NMANAGER_VPC_PIPE_PRESCALE3_SOF_STA_LEN    1
#define VPC_TOP_NMANAGER_VPC_PIPE_PRESCALE3_SOF_STA_OFFSET 3
#define VPC_TOP_NMANAGER_VPC_PIPE_PRESCALE2_SOF_STA_LEN    1
#define VPC_TOP_NMANAGER_VPC_PIPE_PRESCALE2_SOF_STA_OFFSET 2
#define VPC_TOP_NMANAGER_VPC_PIPE_PRESCALE1_SOF_STA_LEN    1
#define VPC_TOP_NMANAGER_VPC_PIPE_PRESCALE1_SOF_STA_OFFSET 1
#define VPC_TOP_NMANAGER_VPC_PIPE_PRECROP_EOP_STA_LEN      1
#define VPC_TOP_NMANAGER_VPC_PIPE_PRECROP_EOP_STA_OFFSET   0

#define VPC_TOP_NMANAGER_VPC_CVDR_VP_WR_EOL_MASK_LEN    5
#define VPC_TOP_NMANAGER_VPC_CVDR_VP_WR_EOL_MASK_OFFSET 19
#define VPC_TOP_NMANAGER_VPC_CVDR_VP_WR_EOF_MASK_LEN    5
#define VPC_TOP_NMANAGER_VPC_CVDR_VP_WR_EOF_MASK_OFFSET 14
#define VPC_TOP_NMANAGER_VPC_CVDR_VP_WR_SOF_MASK_LEN    5
#define VPC_TOP_NMANAGER_VPC_CVDR_VP_WR_SOF_MASK_OFFSET 9
#define VPC_TOP_NMANAGER_VPC_CVDR_VP_RD_EOL_MASK_LEN    3
#define VPC_TOP_NMANAGER_VPC_CVDR_VP_RD_EOL_MASK_OFFSET 6
#define VPC_TOP_NMANAGER_VPC_CVDR_VP_RD_EOF_MASK_LEN    3
#define VPC_TOP_NMANAGER_VPC_CVDR_VP_RD_EOF_MASK_OFFSET 3
#define VPC_TOP_NMANAGER_VPC_CVDR_VP_RD_SOF_MASK_LEN    3
#define VPC_TOP_NMANAGER_VPC_CVDR_VP_RD_SOF_MASK_OFFSET 0

#define VPC_TOP_NMANAGER_VPC_EOF_INT1_MASK_LEN              1
#define VPC_TOP_NMANAGER_VPC_EOF_INT1_MASK_OFFSET           12
#define VPC_TOP_NMANAGER_VPC_EOF_INT2_MASK_LEN              1
#define VPC_TOP_NMANAGER_VPC_EOF_INT2_MASK_OFFSET           11
#define VPC_TOP_NMANAGER_VPC_RDMA_FRAME_END_MASK_LEN        1
#define VPC_TOP_NMANAGER_VPC_RDMA_FRAME_END_MASK_OFFSET     10
#define VPC_TOP_NMANAGER_VPC_PIPE_POSTCROP2_EOP_MASK_LEN    1
#define VPC_TOP_NMANAGER_VPC_PIPE_POSTCROP2_EOP_MASK_OFFSET 9
#define VPC_TOP_NMANAGER_VPC_PIPE_YUVSCALE2_EOF_MASK_LEN    1
#define VPC_TOP_NMANAGER_VPC_PIPE_YUVSCALE2_EOF_MASK_OFFSET 8
#define VPC_TOP_NMANAGER_VPC_PIPE_YUVSCALE2_SOF_MASK_LEN    1
#define VPC_TOP_NMANAGER_VPC_PIPE_YUVSCALE2_SOF_MASK_OFFSET 7
#define VPC_TOP_NMANAGER_VPC_PIPE_POSTCROP1_EOP_MASK_LEN    1
#define VPC_TOP_NMANAGER_VPC_PIPE_POSTCROP1_EOP_MASK_OFFSET 6
#define VPC_TOP_NMANAGER_VPC_PIPE_YUVSCALE_EOF_MASK_LEN     1
#define VPC_TOP_NMANAGER_VPC_PIPE_YUVSCALE_EOF_MASK_OFFSET  5
#define VPC_TOP_NMANAGER_VPC_PIPE_YUVSCALE_SOF_MASK_LEN     1
#define VPC_TOP_NMANAGER_VPC_PIPE_YUVSCALE_SOF_MASK_OFFSET  4
#define VPC_TOP_NMANAGER_VPC_PIPE_PRESCALE3_SOF_MASK_LEN    1
#define VPC_TOP_NMANAGER_VPC_PIPE_PRESCALE3_SOF_MASK_OFFSET 3
#define VPC_TOP_NMANAGER_VPC_PIPE_PRESCALE2_SOF_MASK_LEN    1
#define VPC_TOP_NMANAGER_VPC_PIPE_PRESCALE2_SOF_MASK_OFFSET 2
#define VPC_TOP_NMANAGER_VPC_PIPE_PRESCALE1_SOF_MASK_LEN    1
#define VPC_TOP_NMANAGER_VPC_PIPE_PRESCALE1_SOF_MASK_OFFSET 1
#define VPC_TOP_NMANAGER_VPC_PIPE_PRECROP_EOP_MASK_LEN      1
#define VPC_TOP_NMANAGER_VPC_PIPE_PRECROP_EOP_MASK_OFFSET   0

#define VPC_TOP_NMANAGER_VPC_CVDR_VP_WR_EOL_MASK_STA_LEN    5
#define VPC_TOP_NMANAGER_VPC_CVDR_VP_WR_EOL_MASK_STA_OFFSET 19
#define VPC_TOP_NMANAGER_VPC_CVDR_VP_WR_EOF_MASK_STA_LEN    5
#define VPC_TOP_NMANAGER_VPC_CVDR_VP_WR_EOF_MASK_STA_OFFSET 14
#define VPC_TOP_NMANAGER_VPC_CVDR_VP_WR_SOF_MASK_STA_LEN    5
#define VPC_TOP_NMANAGER_VPC_CVDR_VP_WR_SOF_MASK_STA_OFFSET 9
#define VPC_TOP_NMANAGER_VPC_CVDR_VP_RD_EOL_MASK_STA_LEN    3
#define VPC_TOP_NMANAGER_VPC_CVDR_VP_RD_EOL_MASK_STA_OFFSET 6
#define VPC_TOP_NMANAGER_VPC_CVDR_VP_RD_EOF_MASK_STA_LEN    3
#define VPC_TOP_NMANAGER_VPC_CVDR_VP_RD_EOF_MASK_STA_OFFSET 3
#define VPC_TOP_NMANAGER_VPC_CVDR_VP_RD_SOF_MASK_STA_LEN    3
#define VPC_TOP_NMANAGER_VPC_CVDR_VP_RD_SOF_MASK_STA_OFFSET 0

#define VPC_TOP_NMANAGER_VPC_EOF_INT1_MASK_STA_LEN              1
#define VPC_TOP_NMANAGER_VPC_EOF_INT1_MASK_STA_OFFSET           12
#define VPC_TOP_NMANAGER_VPC_EOF_INT2_MASK_STA_LEN              1
#define VPC_TOP_NMANAGER_VPC_EOF_INT2_MASK_STA_OFFSET           11
#define VPC_TOP_NMANAGER_VPC_RDMA_FRAME_END_MASK_STA_LEN        1
#define VPC_TOP_NMANAGER_VPC_RDMA_FRAME_END_MASK_STA_OFFSET     10
#define VPC_TOP_NMANAGER_VPC_PIPE_POSTCROP2_EOP_MASK_STA_LEN    1
#define VPC_TOP_NMANAGER_VPC_PIPE_POSTCROP2_EOP_MASK_STA_OFFSET 9
#define VPC_TOP_NMANAGER_VPC_PIPE_YUVSCALE2_EOF_MASK_STA_LEN    1
#define VPC_TOP_NMANAGER_VPC_PIPE_YUVSCALE2_EOF_MASK_STA_OFFSET 8
#define VPC_TOP_NMANAGER_VPC_PIPE_YUVSCALE2_SOF_MASK_STA_LEN    1
#define VPC_TOP_NMANAGER_VPC_PIPE_YUVSCALE2_SOF_MASK_STA_OFFSET 7
#define VPC_TOP_NMANAGER_VPC_PIPE_POSTCROP1_EOP_MASK_STA_LEN    1
#define VPC_TOP_NMANAGER_VPC_PIPE_POSTCROP1_EOP_MASK_STA_OFFSET 6
#define VPC_TOP_NMANAGER_VPC_PIPE_YUVSCALE_EOF_MASK_STA_LEN     1
#define VPC_TOP_NMANAGER_VPC_PIPE_YUVSCALE_EOF_MASK_STA_OFFSET  5
#define VPC_TOP_NMANAGER_VPC_PIPE_YUVSCALE_SOF_MASK_STA_LEN     1
#define VPC_TOP_NMANAGER_VPC_PIPE_YUVSCALE_SOF_MASK_STA_OFFSET  4
#define VPC_TOP_NMANAGER_VPC_PIPE_PRESCALE3_SOF_MASK_STA_LEN    1
#define VPC_TOP_NMANAGER_VPC_PIPE_PRESCALE3_SOF_MASK_STA_OFFSET 3
#define VPC_TOP_NMANAGER_VPC_PIPE_PRESCALE2_SOF_MASK_STA_LEN    1
#define VPC_TOP_NMANAGER_VPC_PIPE_PRESCALE2_SOF_MASK_STA_OFFSET 2
#define VPC_TOP_NMANAGER_VPC_PIPE_PRESCALE1_SOF_MASK_STA_LEN    1
#define VPC_TOP_NMANAGER_VPC_PIPE_PRESCALE1_SOF_MASK_STA_OFFSET 1
#define VPC_TOP_NMANAGER_VPC_PIPE_PRECROP_EOP_MASK_STA_LEN      1
#define VPC_TOP_NMANAGER_VPC_PIPE_PRECROP_EOP_MASK_STA_OFFSET   0

#define VPC_TOP_NMANAGER_VPC_CVDR_VP_WR_EOL_CLR_LEN    5
#define VPC_TOP_NMANAGER_VPC_CVDR_VP_WR_EOL_CLR_OFFSET 19
#define VPC_TOP_NMANAGER_VPC_CVDR_VP_WR_EOF_CLR_LEN    5
#define VPC_TOP_NMANAGER_VPC_CVDR_VP_WR_EOF_CLR_OFFSET 14
#define VPC_TOP_NMANAGER_VPC_CVDR_VP_WR_SOF_CLR_LEN    5
#define VPC_TOP_NMANAGER_VPC_CVDR_VP_WR_SOF_CLR_OFFSET 9
#define VPC_TOP_NMANAGER_VPC_CVDR_VP_RD_EOL_CLR_LEN    3
#define VPC_TOP_NMANAGER_VPC_CVDR_VP_RD_EOL_CLR_OFFSET 6
#define VPC_TOP_NMANAGER_VPC_CVDR_VP_RD_EOF_CLR_LEN    3
#define VPC_TOP_NMANAGER_VPC_CVDR_VP_RD_EOF_CLR_OFFSET 3
#define VPC_TOP_NMANAGER_VPC_CVDR_VP_RD_SOF_CLR_LEN    3
#define VPC_TOP_NMANAGER_VPC_CVDR_VP_RD_SOF_CLR_OFFSET 0

#define VPC_TOP_NMANAGER_VPC_EOF_INT1_CLR_LEN              1
#define VPC_TOP_NMANAGER_VPC_EOF_INT1_CLR_OFFSET           12
#define VPC_TOP_NMANAGER_VPC_EOF_INT2_CLR_LEN              1
#define VPC_TOP_NMANAGER_VPC_EOF_INT2_CLR_OFFSET           11
#define VPC_TOP_NMANAGER_VPC_RDMA_FRAME_END_CLR_LEN        1
#define VPC_TOP_NMANAGER_VPC_RDMA_FRAME_END_CLR_OFFSET     10
#define VPC_TOP_NMANAGER_VPC_PIPE_POSTCROP2_EOP_CLR_LEN    1
#define VPC_TOP_NMANAGER_VPC_PIPE_POSTCROP2_EOP_CLR_OFFSET 9
#define VPC_TOP_NMANAGER_VPC_PIPE_YUVSCALE2_EOF_CLR_LEN    1
#define VPC_TOP_NMANAGER_VPC_PIPE_YUVSCALE2_EOF_CLR_OFFSET 8
#define VPC_TOP_NMANAGER_VPC_PIPE_YUVSCALE2_SOF_CLR_LEN    1
#define VPC_TOP_NMANAGER_VPC_PIPE_YUVSCALE2_SOF_CLR_OFFSET 7
#define VPC_TOP_NMANAGER_VPC_PIPE_POSTCROP1_EOP_CLR_LEN    1
#define VPC_TOP_NMANAGER_VPC_PIPE_POSTCROP1_EOP_CLR_OFFSET 6
#define VPC_TOP_NMANAGER_VPC_PIPE_YUVSCALE_EOF_CLR_LEN     1
#define VPC_TOP_NMANAGER_VPC_PIPE_YUVSCALE_EOF_CLR_OFFSET  5
#define VPC_TOP_NMANAGER_VPC_PIPE_YUVSCALE_SOF_CLR_LEN     1
#define VPC_TOP_NMANAGER_VPC_PIPE_YUVSCALE_SOF_CLR_OFFSET  4
#define VPC_TOP_NMANAGER_VPC_PIPE_PRESCALE3_SOF_CLR_LEN    1
#define VPC_TOP_NMANAGER_VPC_PIPE_PRESCALE3_SOF_CLR_OFFSET 3
#define VPC_TOP_NMANAGER_VPC_PIPE_PRESCALE2_SOF_CLR_LEN    1
#define VPC_TOP_NMANAGER_VPC_PIPE_PRESCALE2_SOF_CLR_OFFSET 2
#define VPC_TOP_NMANAGER_VPC_PIPE_PRESCALE1_SOF_CLR_LEN    1
#define VPC_TOP_NMANAGER_VPC_PIPE_PRESCALE1_SOF_CLR_OFFSET 1
#define VPC_TOP_NMANAGER_VPC_PIPE_PRECROP_EOP_CLR_LEN      1
#define VPC_TOP_NMANAGER_VPC_PIPE_PRECROP_EOP_CLR_OFFSET   0

#define VPC_TOP_NMANAGER_VPC_CVDR_VP_WR_EOL_SET_LEN    5
#define VPC_TOP_NMANAGER_VPC_CVDR_VP_WR_EOL_SET_OFFSET 19
#define VPC_TOP_NMANAGER_VPC_CVDR_VP_WR_EOF_SET_LEN    5
#define VPC_TOP_NMANAGER_VPC_CVDR_VP_WR_EOF_SET_OFFSET 14
#define VPC_TOP_NMANAGER_VPC_CVDR_VP_WR_SOF_SET_LEN    5
#define VPC_TOP_NMANAGER_VPC_CVDR_VP_WR_SOF_SET_OFFSET 9
#define VPC_TOP_NMANAGER_VPC_CVDR_VP_RD_EOL_SET_LEN    3
#define VPC_TOP_NMANAGER_VPC_CVDR_VP_RD_EOL_SET_OFFSET 6
#define VPC_TOP_NMANAGER_VPC_CVDR_VP_RD_EOF_SET_LEN    3
#define VPC_TOP_NMANAGER_VPC_CVDR_VP_RD_EOF_SET_OFFSET 3
#define VPC_TOP_NMANAGER_VPC_CVDR_VP_RD_SOF_SET_LEN    3
#define VPC_TOP_NMANAGER_VPC_CVDR_VP_RD_SOF_SET_OFFSET 0

#define VPC_TOP_NMANAGER_VPC_EOF_INT1_SET_LEN              1
#define VPC_TOP_NMANAGER_VPC_EOF_INT1_SET_OFFSET           12
#define VPC_TOP_NMANAGER_VPC_EOF_INT2_SET_LEN              1
#define VPC_TOP_NMANAGER_VPC_EOF_INT2_SET_OFFSET           11
#define VPC_TOP_NMANAGER_VPC_RDMA_FRAME_END_SET_LEN        1
#define VPC_TOP_NMANAGER_VPC_RDMA_FRAME_END_SET_OFFSET     10
#define VPC_TOP_NMANAGER_VPC_PIPE_POSTCROP2_EOP_SET_LEN    1
#define VPC_TOP_NMANAGER_VPC_PIPE_POSTCROP2_EOP_SET_OFFSET 9
#define VPC_TOP_NMANAGER_VPC_PIPE_YUVSCALE2_EOF_SET_LEN    1
#define VPC_TOP_NMANAGER_VPC_PIPE_YUVSCALE2_EOF_SET_OFFSET 8
#define VPC_TOP_NMANAGER_VPC_PIPE_YUVSCALE2_SOF_SET_LEN    1
#define VPC_TOP_NMANAGER_VPC_PIPE_YUVSCALE2_SOF_SET_OFFSET 7
#define VPC_TOP_NMANAGER_VPC_PIPE_POSTCROP1_EOP_SET_LEN    1
#define VPC_TOP_NMANAGER_VPC_PIPE_POSTCROP1_EOP_SET_OFFSET 6
#define VPC_TOP_NMANAGER_VPC_PIPE_YUVSCALE_EOF_SET_LEN     1
#define VPC_TOP_NMANAGER_VPC_PIPE_YUVSCALE_EOF_SET_OFFSET  5
#define VPC_TOP_NMANAGER_VPC_PIPE_YUVSCALE_SOF_SET_LEN     1
#define VPC_TOP_NMANAGER_VPC_PIPE_YUVSCALE_SOF_SET_OFFSET  4
#define VPC_TOP_NMANAGER_VPC_PIPE_PRESCALE3_SOF_SET_LEN    1
#define VPC_TOP_NMANAGER_VPC_PIPE_PRESCALE3_SOF_SET_OFFSET 3
#define VPC_TOP_NMANAGER_VPC_PIPE_PRESCALE2_SOF_SET_LEN    1
#define VPC_TOP_NMANAGER_VPC_PIPE_PRESCALE2_SOF_SET_OFFSET 2
#define VPC_TOP_NMANAGER_VPC_PIPE_PRESCALE1_SOF_SET_LEN    1
#define VPC_TOP_NMANAGER_VPC_PIPE_PRESCALE1_SOF_SET_OFFSET 1
#define VPC_TOP_NMANAGER_VPC_PIPE_PRECROP_EOP_SET_LEN      1
#define VPC_TOP_NMANAGER_VPC_PIPE_PRECROP_EOP_SET_OFFSET   0

#define VPC_TOP_NMANAGER_VPC_RDMA_FRAME_END_MINT1_EN_LEN        1
#define VPC_TOP_NMANAGER_VPC_RDMA_FRAME_END_MINT1_EN_OFFSET     11
#define VPC_TOP_NMANAGER_VPC_PIPE_POSTCROP2_EOP_MINT1_EN_LEN    1
#define VPC_TOP_NMANAGER_VPC_PIPE_POSTCROP2_EOP_MINT1_EN_OFFSET 10
#define VPC_TOP_NMANAGER_VPC_PIPE_YUVSCALE2_EOF_MINT1_EN_LEN    1
#define VPC_TOP_NMANAGER_VPC_PIPE_YUVSCALE2_EOF_MINT1_EN_OFFSET 9
#define VPC_TOP_NMANAGER_VPC_PIPE_POSTCROP1_EOP_MINT1_EN_LEN    1
#define VPC_TOP_NMANAGER_VPC_PIPE_POSTCROP1_EOP_MINT1_EN_OFFSET 8
#define VPC_TOP_NMANAGER_VPC_PIPE_YUVSCALE_EOF_MINT1_EN_LEN     1
#define VPC_TOP_NMANAGER_VPC_PIPE_YUVSCALE_EOF_MINT1_EN_OFFSET  7
#define VPC_TOP_NMANAGER_VPC_PIPE_PRECROP_EOP_MINT1_EN_LEN      1
#define VPC_TOP_NMANAGER_VPC_PIPE_PRECROP_EOP_MINT1_EN_OFFSET   6
#define VPC_TOP_NMANAGER_VPC_CVDR_VP_WR_EOF_MINT1_EN_LEN        4
#define VPC_TOP_NMANAGER_VPC_CVDR_VP_WR_EOF_MINT1_EN_OFFSET     2
#define VPC_TOP_NMANAGER_VPC_CVDR_VP_RD_EOF_MINT1_EN_LEN        2
#define VPC_TOP_NMANAGER_VPC_CVDR_VP_RD_EOF_MINT1_EN_OFFSET     0

#define VPC_TOP_NMANAGER_VPC_RDMA_FRAME_END_MINT2_EN_LEN        1
#define VPC_TOP_NMANAGER_VPC_RDMA_FRAME_END_MINT2_EN_OFFSET     11
#define VPC_TOP_NMANAGER_VPC_PIPE_POSTCROP2_EOP_MINT2_EN_LEN    1
#define VPC_TOP_NMANAGER_VPC_PIPE_POSTCROP2_EOP_MINT2_EN_OFFSET 10
#define VPC_TOP_NMANAGER_VPC_PIPE_YUVSCALE2_EOF_MINT2_EN_LEN    1
#define VPC_TOP_NMANAGER_VPC_PIPE_YUVSCALE2_EOF_MINT2_EN_OFFSET 9
#define VPC_TOP_NMANAGER_VPC_PIPE_POSTCROP1_EOP_MINT2_EN_LEN    1
#define VPC_TOP_NMANAGER_VPC_PIPE_POSTCROP1_EOP_MINT2_EN_OFFSET 8
#define VPC_TOP_NMANAGER_VPC_PIPE_YUVSCALE_EOF_MINT2_EN_LEN     1
#define VPC_TOP_NMANAGER_VPC_PIPE_YUVSCALE_EOF_MINT2_EN_OFFSET  7
#define VPC_TOP_NMANAGER_VPC_PIPE_PRECROP_EOP_MINT2_EN_LEN      1
#define VPC_TOP_NMANAGER_VPC_PIPE_PRECROP_EOP_MINT2_EN_OFFSET   6
#define VPC_TOP_NMANAGER_VPC_CVDR_VP_WR_EOF_MINT2_EN_LEN        4
#define VPC_TOP_NMANAGER_VPC_CVDR_VP_WR_EOF_MINT2_EN_OFFSET     2
#define VPC_TOP_NMANAGER_VPC_CVDR_VP_RD_EOF_MINT2_EN_LEN        2
#define VPC_TOP_NMANAGER_VPC_CVDR_VP_RD_EOF_MINT2_EN_OFFSET     0

#define VPC_TOP_NMANAGER_VPC_EOF_INT1_STA_CMDLST_EN_LEN    1
#define VPC_TOP_NMANAGER_VPC_EOF_INT1_STA_CMDLST_EN_OFFSET 1
#define VPC_TOP_NMANAGER_VPC_EOF_INT2_STA_CMDLST_EN_LEN    1
#define VPC_TOP_NMANAGER_VPC_EOF_INT2_STA_CMDLST_EN_OFFSET 0

#define VPC_TOP_NMANAGER_VPC_S2P_EVEN_WIDTH_ERR_STA_LEN      1
#define VPC_TOP_NMANAGER_VPC_S2P_EVEN_WIDTH_ERR_STA_OFFSET   10
#define VPC_TOP_NMANAGER_VPC_CVDR_AXI_RD_RESP_ERR_STA_LEN    1
#define VPC_TOP_NMANAGER_VPC_CVDR_AXI_RD_RESP_ERR_STA_OFFSET 9
#define VPC_TOP_NMANAGER_VPC_CVDR_AXI_WR_RESP_ERR_STA_LEN    1
#define VPC_TOP_NMANAGER_VPC_CVDR_AXI_WR_RESP_ERR_STA_OFFSET 8
#define VPC_TOP_NMANAGER_VPC_CVDR_AXI_WR_FULL_STA_LEN        1
#define VPC_TOP_NMANAGER_VPC_CVDR_AXI_WR_FULL_STA_OFFSET     7
#define VPC_TOP_NMANAGER_VPC_CVDR_VP_WR_DROPPED_STA_LEN      5
#define VPC_TOP_NMANAGER_VPC_CVDR_VP_WR_DROPPED_STA_OFFSET   2
#define VPC_TOP_NMANAGER_VPC_RDMA_AXI_RD_RESP_ERR_STA_LEN    1
#define VPC_TOP_NMANAGER_VPC_RDMA_AXI_RD_RESP_ERR_STA_OFFSET 1
#define VPC_TOP_NMANAGER_VPC_RDMA_HFBCD_DEC_ERR_STA_LEN      1
#define VPC_TOP_NMANAGER_VPC_RDMA_HFBCD_DEC_ERR_STA_OFFSET   0

#define VPC_TOP_NMANAGER_VPC_S2P_EVEN_WIDTH_ERR_MASK_LEN      1
#define VPC_TOP_NMANAGER_VPC_S2P_EVEN_WIDTH_ERR_MASK_OFFSET   10
#define VPC_TOP_NMANAGER_VPC_CVDR_AXI_RD_RESP_ERR_MASK_LEN    1
#define VPC_TOP_NMANAGER_VPC_CVDR_AXI_RD_RESP_ERR_MASK_OFFSET 9
#define VPC_TOP_NMANAGER_VPC_CVDR_AXI_WR_RESP_ERR_MASK_LEN    1
#define VPC_TOP_NMANAGER_VPC_CVDR_AXI_WR_RESP_ERR_MASK_OFFSET 8
#define VPC_TOP_NMANAGER_VPC_CVDR_AXI_WR_FULL_MASK_LEN        1
#define VPC_TOP_NMANAGER_VPC_CVDR_AXI_WR_FULL_MASK_OFFSET     7
#define VPC_TOP_NMANAGER_VPC_CVDR_VP_WR_DROPPED_MASK_LEN      5
#define VPC_TOP_NMANAGER_VPC_CVDR_VP_WR_DROPPED_MASK_OFFSET   2
#define VPC_TOP_NMANAGER_VPC_RDMA_AXI_RD_RESP_ERR_MASK_LEN    1
#define VPC_TOP_NMANAGER_VPC_RDMA_AXI_RD_RESP_ERR_MASK_OFFSET 1
#define VPC_TOP_NMANAGER_VPC_RDMA_HFBCD_DEC_ERR_MASK_LEN      1
#define VPC_TOP_NMANAGER_VPC_RDMA_HFBCD_DEC_ERR_MASK_OFFSET   0

#define VPC_TOP_NMANAGER_VPC_S2P_EVEN_WIDTH_ERR_MASK_STA_LEN      1
#define VPC_TOP_NMANAGER_VPC_S2P_EVEN_WIDTH_ERR_MASK_STA_OFFSET   10
#define VPC_TOP_NMANAGER_VPC_CVDR_AXI_RD_RESP_ERR_MASK_STA_LEN    1
#define VPC_TOP_NMANAGER_VPC_CVDR_AXI_RD_RESP_ERR_MASK_STA_OFFSET 9
#define VPC_TOP_NMANAGER_VPC_CVDR_AXI_WR_RESP_ERR_MASK_STA_LEN    1
#define VPC_TOP_NMANAGER_VPC_CVDR_AXI_WR_RESP_ERR_MASK_STA_OFFSET 8
#define VPC_TOP_NMANAGER_VPC_CVDR_AXI_WR_FULL_MASK_STA_LEN        1
#define VPC_TOP_NMANAGER_VPC_CVDR_AXI_WR_FULL_MASK_STA_OFFSET     7
#define VPC_TOP_NMANAGER_VPC_CVDR_VP_WR_DROPPED_MASK_STA_LEN      5
#define VPC_TOP_NMANAGER_VPC_CVDR_VP_WR_DROPPED_MASK_STA_OFFSET   2
#define VPC_TOP_NMANAGER_VPC_RDMA_AXI_RD_RESP_ERR_MASK_STA_LEN    1
#define VPC_TOP_NMANAGER_VPC_RDMA_AXI_RD_RESP_ERR_MASK_STA_OFFSET 1
#define VPC_TOP_NMANAGER_VPC_RDMA_HFBCD_DEC_ERR_MASK_STA_LEN      1
#define VPC_TOP_NMANAGER_VPC_RDMA_HFBCD_DEC_ERR_MASK_STA_OFFSET   0

#define VPC_TOP_NMANAGER_VPC_S2P_EVEN_WIDTH_ERR_CLR_LEN      1
#define VPC_TOP_NMANAGER_VPC_S2P_EVEN_WIDTH_ERR_CLR_OFFSET   10
#define VPC_TOP_NMANAGER_VPC_CVDR_AXI_RD_RESP_ERR_CLR_LEN    1
#define VPC_TOP_NMANAGER_VPC_CVDR_AXI_RD_RESP_ERR_CLR_OFFSET 9
#define VPC_TOP_NMANAGER_VPC_CVDR_AXI_WR_RESP_ERR_CLR_LEN    1
#define VPC_TOP_NMANAGER_VPC_CVDR_AXI_WR_RESP_ERR_CLR_OFFSET 8
#define VPC_TOP_NMANAGER_VPC_CVDR_AXI_WR_FULL_CLR_LEN        1
#define VPC_TOP_NMANAGER_VPC_CVDR_AXI_WR_FULL_CLR_OFFSET     7
#define VPC_TOP_NMANAGER_VPC_CVDR_VP_WR_DROPPED_CLR_LEN      5
#define VPC_TOP_NMANAGER_VPC_CVDR_VP_WR_DROPPED_CLR_OFFSET   2
#define VPC_TOP_NMANAGER_VPC_RDMA_AXI_RD_RESP_ERR_CLR_LEN    1
#define VPC_TOP_NMANAGER_VPC_RDMA_AXI_RD_RESP_ERR_CLR_OFFSET 1
#define VPC_TOP_NMANAGER_VPC_RDMA_HFBCD_DEC_ERR_CLR_LEN      1
#define VPC_TOP_NMANAGER_VPC_RDMA_HFBCD_DEC_ERR_CLR_OFFSET   0

#define VPC_TOP_NMANAGER_VPC_S2P_EVEN_WIDTH_ERR_SET_LEN      1
#define VPC_TOP_NMANAGER_VPC_S2P_EVEN_WIDTH_ERR_SET_OFFSET   10
#define VPC_TOP_NMANAGER_VPC_CVDR_AXI_RD_RESP_ERR_SET_LEN    1
#define VPC_TOP_NMANAGER_VPC_CVDR_AXI_RD_RESP_ERR_SET_OFFSET 9
#define VPC_TOP_NMANAGER_VPC_CVDR_AXI_WR_RESP_ERR_SET_LEN    1
#define VPC_TOP_NMANAGER_VPC_CVDR_AXI_WR_RESP_ERR_SET_OFFSET 8
#define VPC_TOP_NMANAGER_VPC_CVDR_AXI_WR_FULL_SET_LEN        1
#define VPC_TOP_NMANAGER_VPC_CVDR_AXI_WR_FULL_SET_OFFSET     7
#define VPC_TOP_NMANAGER_VPC_CVDR_VP_WR_DROPPED_SET_LEN      5
#define VPC_TOP_NMANAGER_VPC_CVDR_VP_WR_DROPPED_SET_OFFSET   2
#define VPC_TOP_NMANAGER_VPC_RDMA_AXI_RD_RESP_ERR_SET_LEN    1
#define VPC_TOP_NMANAGER_VPC_RDMA_AXI_RD_RESP_ERR_SET_OFFSET 1
#define VPC_TOP_NMANAGER_VPC_RDMA_HFBCD_DEC_ERR_SET_LEN      1
#define VPC_TOP_NMANAGER_VPC_RDMA_HFBCD_DEC_ERR_SET_OFFSET   0

#define VPC_TOP_NMANAGER_CFG_AWADDR_EXT_LEN    32
#define VPC_TOP_NMANAGER_CFG_AWADDR_EXT_OFFSET 0

#define VPC_TOP_NMANAGER_CFG_ARADDR_EXT_LEN    32
#define VPC_TOP_NMANAGER_CFG_ARADDR_EXT_OFFSET 0

#define VPC_TOP_NMANAGER_CFG_AWUSER_L_LEN    32
#define VPC_TOP_NMANAGER_CFG_AWUSER_L_OFFSET 0

#define VPC_TOP_NMANAGER_CFG_AWUSER_M_LEN    32
#define VPC_TOP_NMANAGER_CFG_AWUSER_M_OFFSET 0

#define VPC_TOP_NMANAGER_CFG_AWUSER_H_LEN    32
#define VPC_TOP_NMANAGER_CFG_AWUSER_H_OFFSET 0

#define VPC_TOP_NMANAGER_CFG_ARUSER_L_LEN    32
#define VPC_TOP_NMANAGER_CFG_ARUSER_L_OFFSET 0

#define VPC_TOP_NMANAGER_CFG_ARUSER_M_LEN    32
#define VPC_TOP_NMANAGER_CFG_ARUSER_M_OFFSET 0

#define VPC_TOP_NMANAGER_CFG_ARUSER_H_LEN    32
#define VPC_TOP_NMANAGER_CFG_ARUSER_H_OFFSET 0

#define VPC_TOP_NMANAGER_CFG_ARQOS_EN_LEN    1
#define VPC_TOP_NMANAGER_CFG_ARQOS_EN_OFFSET 25
#define VPC_TOP_NMANAGER_CFG_AWQOS_EN_LEN    1
#define VPC_TOP_NMANAGER_CFG_AWQOS_EN_OFFSET 24
#define VPC_TOP_NMANAGER_CFG_ARQOS_LEN       4
#define VPC_TOP_NMANAGER_CFG_ARQOS_OFFSET    20
#define VPC_TOP_NMANAGER_CFG_AWQOS_LEN       4
#define VPC_TOP_NMANAGER_CFG_AWQOS_OFFSET    16
#define VPC_TOP_NMANAGER_CFG_ARCACHE_LEN     4
#define VPC_TOP_NMANAGER_CFG_ARCACHE_OFFSET  8
#define VPC_TOP_NMANAGER_CFG_AWCACHE_LEN     4
#define VPC_TOP_NMANAGER_CFG_AWCACHE_OFFSET  0

#define VPC_TOP_NMANAGER_CFG_SHIM_CTRL_LEN    32
#define VPC_TOP_NMANAGER_CFG_SHIM_CTRL_OFFSET 0

#define VPC_TOP_NMANAGER_HFBCD_DEBUG_OUT1_LEN    32
#define VPC_TOP_NMANAGER_HFBCD_DEBUG_OUT1_OFFSET 0

#define VPC_TOP_NMANAGER_HFBCD_DEBUG_OUT2_LEN    32
#define VPC_TOP_NMANAGER_HFBCD_DEBUG_OUT2_OFFSET 0

#define VPC_TOP_NMANAGER_LINEBUF_DEBUG_INFO1_LEN    32
#define VPC_TOP_NMANAGER_LINEBUF_DEBUG_INFO1_OFFSET 0

#define VPC_TOP_NMANAGER_LINEBUF_DEBUG_INFO2_LEN    32
#define VPC_TOP_NMANAGER_LINEBUF_DEBUG_INFO2_OFFSET 0

#define VPC_TOP_NMANAGER_LINEBUF_DEBUG_INFO3_LEN    32
#define VPC_TOP_NMANAGER_LINEBUF_DEBUG_INFO3_OFFSET 0

#define VPC_TOP_NMANAGER_LINEBUF_DEBUG_INFO4_LEN    32
#define VPC_TOP_NMANAGER_LINEBUF_DEBUG_INFO4_OFFSET 0

#define VPC_TOP_NMANAGER_CMDLST_DEBUG_OUT_LEN    16
#define VPC_TOP_NMANAGER_CMDLST_DEBUG_OUT_OFFSET 0

#define VPC_TOP_NMANAGER_SP_RAM_CTRL_LEN    32
#define VPC_TOP_NMANAGER_SP_RAM_CTRL_OFFSET 0

#define VPC_TOP_NMANAGER_TP_RAM_CTRL_LEN    32
#define VPC_TOP_NMANAGER_TP_RAM_CTRL_OFFSET 0

#endif // __VPC_TOP_NMANAGER_REG_OFFSET_FIELD_H__
